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Within the semiconductor ATE industry, the terms "multi-site", "concurrent", and "parallel" testing do take on slightly different meanings. For example, concurrent testing can refer to the simultaneous testing of identical blocks of circuitry within a single device. This is in contrast to multi-site testing which may refer to multiple devices tested in parallel. Regardless, in general, these three terms express state-of-the-art test technologies by ATE manufacturing companies like Teradyne, Agilent, Advantest, Aeroflex, Credence, Eagle, LTX, Nextest, and Verigy.
As the technology of SOC/SIP multi-site testing develops, the process will necessarily move toward increased channel integration per site with improved probing, handling, and signal integrity and/or EMI techniques. Especially as SOC/SIP methods are used for radio frequency (RF) embedded solutions. Design-for-Test (DFT) principles and techniques will have to play an even more significant role, particularly in RF applications where the number of sites for wafer/package tests are as low as 2/4, compared to 256+ for memory.
But whether the site count is low or high, the current metric of effectiveness on cost is the efficiency of the multi-site test. For example, if a multi-site test takes 100mS for 10 sites and has an efficiency of 100%, then this is also the equivalent time that it would take to perform a single-site test. Typical multi-site test of SOC/SIP devices yield efficiencies greater than 80%. The theoretical efficiency is a function of the number of sites, the time for a single-site test, and the multi-site time.
In the discussion above, SOCs and SIPs have been grouped as though they share common testing methodology. Actually, this is not the case. SOCs integrate several like-vendor blocks in the SOC device, which is in contrast to, SIPs that use several unlike-vendor blocks in the SIP device, the two test strategies are different. And speaking of strategies, it has now been "conclusively" established that multi-site (parallel) testing provides a lower cost of test than low-cost ATE, the proof is in the product line of ATE manufacturing companies.
There are a variety of strategies used in multi-site testing. One strategy uses dedicated hardware (single microcontroller) for each Device-Under-Test (DUT) or site. Another strategy uses a single system computer but with operating software that exploits the multiprocessor multi-threading (analogous to multi-tasking) capability by assigning a thread to each DUT. While still another strategy uses a single system computer to address the sites in near serial fashion. Regardless, all strategies must make provisions (via extra hardware or software) for shared system resources, such as instrumentation, system data bus, control bus, etc.
SOC/SIP multi-site testing involve low site counts, unlike "dumb" memory that has a high site count. To reduce test time in low site counts of complex devices, these "smart" devices are embedded with Built-in-Test (BIT) to create a test-hybrid composed of x% multi-site ATE head-driven testing and y% BIT for 100% relative test coverage. This strategy creates a future dilemma. What happens should y ever begin to approach 100? Would the industry transform itself from the outside-in and turn a ton of metal into a speck of highly coded sand to produce Self-conscious self-testing devices (SCSTs)? Perhaps the ITRS (International Technology Roadmap for Semiconductors) should expand their time horizon to address this fork on the road.
|This article is licensed under the GNU Free Documentation License. It uses material from the Wikipedia article "Multi-site_test". A list of authors is available in Wikipedia.|