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Silicon on insulator



Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improve performance.[1] SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices [2]. The precise thickness of the insulating layer and topmost silicon layer also vary widely with application. The first implementation of SOI was announced by IBM in August 1998.[3]

Additional recommended knowledge

Contents

Industry need

The implementation of SOI technology is one of several manufacturing strategies employed to allow the continued miniaturization of microlectronic devices, colloquially referred to as extending Moore's Law. Reported benefits of SOI technology relative to conventional silicon (bulk CMOS) processing include:

  • Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at matched performance.
  • Resistance to latchup due to complete isolation of the n- and p- well structures.

From a manufacturing perspective, SOI substrates are compatible with most conventional fab processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10 - 15% increase to total manufacturing costs.[4]

Manufacture of SOI wafers

SiO2-based SOI wafers can be produced by several methods:

 

  • Wafer Bonding[8] [9] - the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
    • One prominent example of a wafer bonding process is the Smart Cut™ method developed by the French firm Soitec which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
    • NanoCleave™ is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and silicon-germanium alloy.[10]
    • ELTRAN™ is a technology developed by Canon which sports porous silicon and water cut.[11]
  • Seed methods[12] - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.

An exhaustive review of these various manufacturing processes may be found in reference [1]

 

Use in the microelectronics industry

Examples of microprocessors built on SOI technology include AMD's 130 nm, 90 nm and 65 nm single, dual and quad core processors since 2001. [13] Freescale adopted SOI in their PowerPC 7455 CPU in late 2001, currently Freescale is shipping SOI products in 180nm, 130nm, 90nm and 65nm lines.[14] IBM began to use SOI in PowerPC G4 7455 chips since late 2000. [15] The 90 nm PowerPC-based processors used in the Xbox 360, PlayStation 3 and Wii use SOI technology as well. Competitive offerings from Intel, however, such as the 65 nm Core 2 and Core 2 Duo microprocessors, are built using conventional bulk CMOS technology. Intel's new 45 nm process will continue to use conventional technology. However, Intel made a claim of single-chip silicon laser based on SOI. [16]

On the foundry side, TSMC claimed no customer wanted SOI.[17] But Chartered Semiconductor devoted a whole fab to SOI.[18]

References

  1. ^ a b Celler, G.K., Cristoloveanu, S. J App Phys, 93, 4955 (2003)
  2. ^ SOI design: analog, memory and digital techniques by Andrew Marshall & Sreedhar Natarajan, Kluwer Academic, 2002, ISBN 0-7923-7640-4
  3. ^ http://www-03.ibm.com/press/us/en/pressrelease/2521.wss
  4. ^ http://news.com.com/IBM+touts+chipmaking+technology/2100-1001_3-254983.html
  5. ^ http://www.google.com/patents?vid=5888297
  6. ^ http://www.google.com/patents?vid=USPAT5061642
  7. ^ http://www.ibis.com/simox.htm
  8. ^ "SemiConductor Wafer Bonding: Science and Technology" by Q.-Y. Tong & U. Gösele, Wiley-Interscience, 1998, ISBN:978-0471574811
  9. ^ http://www.google.com/patents?vid=4771016
  10. ^ http://www.sigen.com/
  11. ^ http://www.jsapi.jsap.or.jp/Pdf/Number04/CuttingEdge2.pdf
  12. ^ http://www.google.com/patents?q=5417180&btnG=Search+Patents
  13. ^ http://chip-architect.com/news/2000_11_07_process_130_nm.html
  14. ^ http://www.freescale.com/webapp/sps/site/overview.jsp?nodeId=0121000303#soi
  15. ^ http://titancity.com/articles/ppc.html
  16. ^ http://www.eetasia.com/ART_8800359617_499481,499482.HTM
  17. ^ http://www.fabtech.org/content/view/1698/74/
  18. ^ http://www.charteredsemi.com/media/corp/2006n/20060420_IBM_SOI.asp
 
This article is licensed under the GNU Free Documentation License. It uses material from the Wikipedia article "Silicon_on_insulator". A list of authors is available in Wikipedia.
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