To use all functions of this page, please activate cookies in your browser.
With an accout for my.chemeurope.com you can always see everything at a glance – and you can configure your own website and individual newsletter.
- My watch list
- My saved searches
- My saved topics
- My newsletter
The term "die shrink" (sometimes "optical shrink") refers to a simple semiconductor scaling of semiconductor devices, mainly transistors. The act of shrinking a die is to create a somewhat identical circuitry using a more advanced fabrication process, usually involves an advance of lithographic node. This reduces overall costs of a chip firm as the lack of major architectural changes of the processor designed, reducing the R&D cost, while at the same time allowing more processor dies to be manufactured on the same piece of silicon wafer, resulting in more revenues as per more products sold.
Additional recommended knowledge
"Die shrink" is popular among semiconductor firms, such as Intel, AMD (including the former ATI) and NVIDIA for enriching their product lines. Recent examples includes the codenamed Cedar Mill Pentium 4 processors (from 90 nm CMOS to 65 nm CMOS) and Penryn Core 2 processors (from 65 nm CMOS to 45 nm CMOS), the codenamed Brisbane Athlon 64 X2 processors (from 90 nm SOI to 65 nm SOI), and various generations of GPUs from both ATI and NVIDIA.
In CPU fabrications, it is noted that a "die shrink" always involves in an advance to a lithographic node as defined by ITRS (for example, 600 nm, 350 nm, 250 nm, 180 nm, 130 nm, 90 nm to 65 nm then 45 nm nodes and so on), while for GPU manufacturing, the "die shrink" usually first involves in shrink the die on a node not defined by the ITRS (for instance the 150 nm, 110 nm, 80 nm and 55 nm nodes) which is a stopgap between two ITRS defined lithographic nodes, and then further shrink to the lower ITRS defined nodes, this helps saving further R&D costs.
"Die shrink" is benefitial to the end users as well, as shrinking a die reduces the current leakage in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumptions, increased performance headrooms, and lowered prices.
|This article is licensed under the GNU Free Documentation License. It uses material from the Wikipedia article "Die_shrink". A list of authors is available in Wikipedia.|