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Multiple patterning

Double patterning, or, more generally, multiple patterning, is a class of technologies developed for photolithography to enhance the feature density. In the semiconductor industry, double patterning may be used as early as the 65 nm node and may be a primary lithography technique for the 32 nm node. It can in principle be extended to the 22 nm node as well.

There are several types of double patterning. The four most common types are: double exposure, spacer mask, heterogeneous mask, and intermediate pattern accumulation. It is expected that with appropriate iterations of double patterning techniques multiple patterning may be achieved.


Double exposure

Double exposure is a sequence of two separate exposures of the same photoresist layer using two different photomasks. This technique is commonly used for patterns in the same layer which look very different or have incompatible densities or pitches. In one important case, the two exposures may each consist of lines which are oriented in one or the other of two usually perpendicular directions. This allows the decomposition of two-dimensional patterns into two one-dimensional patterns which are easier to print. This is the basis of DDL technology from Brion, a subsidiary of ASML. The sum of the exposures cannot improve the minimum resolution limit unless the photoresist response is not a simple addition of the two exposures. The double exposure technique allows manufacturability of minimum pitch features in a layout that may contain a variety of features. The 65 nm node saw the introduction of alternating phase-shift masks in manufacturing. This technology is typically a double exposure approach. As long as double exposure can be used effectively and is kept within alignment tolerances, it is the preferred patterning approach since it does not require additional follow-up process steps.

Spacer mask

A spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.

The spacer approach is unique in that with one lithographic exposure, the pitch can be halved indefinitely with a succession of spacer formation and pattern transfer processes. This conveniently avoids the serious issue of overlay between successive exposures. The spacer lithography technique has most frequently been applied in patterning fins for FinFETs.

As spacer materials are commonly hardmask materials, their post-etch pattern quality tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness[1].

The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other[2].

Heterogeneous mask

A heterogeneous mask approach is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample. This second layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is therefore a set of photoresist features in between hardmask features, which can be transferred into the final layer underneath. This allows a doubling of feature density. The Interuniversity Microelectronics Centre (IMEC, Belgium) recently used this approach to pattern the gate level for its 32 nm half-pitch demonstration[1].

A concern with the use of this approach is the discrepancy and delay between the second photoresist pattern and the first hardmask pattern, resulting in an additional source of variation.

Intermediate pattern accumulation

A "brute force" approach, intermediate pattern accumulation involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.

A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography [2].

As with the heterogeneous approach, any discrepancy among the different interleaved patterns would be a source of feature-to-feature variation.


Three of the above approaches (spacer mask, heterogeneous mask, intermediate pattern accumulation) offer the advantage of stepper/scanner re-use for more than one generation, by allowing half-pitch to shrink practically indefinitely. The exposure k1 factor (ratio of imaged half-pitch to optical resolution limit) need no longer decrease and in fact is allowed to increase. The minimum photomask feature size similarly need no longer decrease and can also increase, since it is possible to use other techniques to reduce the wafer feature size, such as trimming, chemical shrinks, thermal reflow, or shrink assist films.


With double or multiple patterning, there are several concerns that have made earlier introduction unattractive.

The tool throughput is reduced by multiple patterning, to the extent that the same pattern will require multiple passes to get printed in full.

Overlay error is a more significant concern, since the positioning of a second feature relative to a first determines the spacing size.

A third concern is increased cost due to higher consumption of materials and tool time, as well as new processes required for multiple patterning. However, multiple patterning can actually allow for some mask cost reduction (no need for phase-shift masks or EUV multilayers) as well as capital expenditure reduction (tool re-use). Alternatively, multiple patterning with cheaper techniques such as nanoimprint lithography may be able to reduce costs further.

Since the target feature size is still being reduced, it is important to maintain tighter tolerances expected of smaller feature sizes. For this reason, the lithographic imaging process is still important, and in fact is further burdened with the use of double or multiple patterning. As an overly simplified example, a 100 nm process with a 10 nm process window may have to be tightened to a 5 nm process window before application to a 50 nm process using a double patterning strategy.

Finally, the yield of a multiple patterning process can be expected to be lower than the original single patterning process. For the commonly cited example of double patterning using two interleaving masks, the overall yield is the product of overlay yield, first mask yield, and second mask yield.

Commercial viability

Due to its rather straightforward application, without the need to change the infrastructure, multiple patterning is not expected to encounter any insurmountable technical or commercialization barriers. Despite the cost and throughput concerns, double patterning has recently received more attention and interest, largely due to the fact that the maximum numerical aperture (~0.93 in air and ~1.35 in water) for an optical lithography system has been reached. At the VLSI Technology Symposium in 2007, Samsung reported on a 38 nm half-pitch NAND Flash cell made using dry 193 nm lithography and double patterning on a few critical layers.

Multiple patterning has emerged as a potential way of extending the resolution capability of currently available lithography tools. Due to this ability to use coarse patterns to define finer patterns, it offers an immediate opportunity to achieve resolution below 30 nm without the need to address the technical challenges of expensive current or next-generation lithography technologies such as EUV or phase-shift masks. The half-pitch table below demonstrates the potential of double patterning and twice-applied double patterning (e.g., two exposures + spacer approach) to go beyond 22 nm half-pitch.

193 nm tool N.A. easy single patterning (k1=0.5) strongly enhanced single patterning (k1=0.3) easy double patterning (k1=0.25) strongly enhanced double patterning (k1=0.15) twice-applied double patterning (k1=0.075)
0.93 104 nm 62 nm 52 nm 31 nm 16 nm
1.2 (water) 80 nm 48 nm 40 nm 24 nm 12 nm
1.35 (water) 71 nm 43 nm 36 nm 21 nm 11 nm
1.55 (theoretical high-index) 62 nm 37 nm 31 nm 19 nm 9 nm

As of October 2007, double patterning is the leading technology targeted for 32 nm half-pitch patterning. Using self-aligned double patterning technology, Samsung has produced 30 nm 64 Gb NAND flash devices.[3] Presumably, with a second round of application of this double patterning, a 15 nm NAND flash design rule is already accessible in principle.


  1. ^ X. Hua et al., J. Vac. Sci. Tech. B, vol. 24, pp. 1850-1858 (2006).
  2. ^ Y-K Choi et al., J. Phys. Chem. B, vol. 107, pp. 3340-3343 (2003).
  3. ^ C. Taylor, "Samsung intros 64-Gbit MLC NAND chip," Electronic News, October 23, 2007.
This article is licensed under the GNU Free Documentation License. It uses material from the Wikipedia article "Multiple_patterning". A list of authors is available in Wikipedia.
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