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45 nanometer

CMOS manufacturing

The 45 nanometer (45 nm) process is the next milestone (commercially viable as of November 2007) in semiconductor fabrication. Intel started mass producing 45 nm chips in November 2007, AMD is targeting 45 nm production in 2008, while IBM, Infineon, Samsung, and Chartered Semiconductor have already completed a common 45 nm process platform. By the end of 2008, SMIC will be the first China-based semiconductor company to move to 45 nm, having licensed the bulk 45 nm process from IBM.

Per ITRS, the 45 nm technology node should have significantly tighter specifications than the current 65 nm node. '45 nm' itself should refer to the average half-pitch of a memory cell manufactured at that technology level.

Many critical feature sizes are smaller than the wavelength of light used for lithography, i.e., 193 nm and/or 248 nm. A variety of techniques, such as larger lenses, are used to make sub-wavelength features. Double patterning may also be introduced to assist in shrinking distances between features, especially if dry lithography is used. It is expected that more layers will be patterned with 193 nm wavelength at the 45 nm node. Moving previously loose layers (such as Metal 4 and Metal 5) from 248 nm to 193 nm wavelength is expected to continue, which will likely further drive costs upward, due to difficulties with 193 nm photoresists.

Intel stated in 2003 that high-k gate dielectrics may be introduced at the 45 nm node to reduce gate leakage current. Chipmakers have since then voiced concerns about introducing these new materials into the gate stack. As of 2007, however, both IBM and Intel have announced that they have high-k and metal gate solutions, which Intel considers to be a fundamental change in transistor design.[1]


Technology demos

  • In 2004, TSMC demonstrated a 0.296 square micrometer 45 nm SRAM cell. Such a prototype is useful for characterizing future technology, but cannot be mass produced as it is manufactured using fundamentally different techniques.
  • In January 2006, Intel demonstrated a 0.346 square micrometers 45 nm node SRAM cell.
  • In April 2006, AMD demonstrated a 0.370 square micrometer 45 nm SRAM cell.
  • In June 2006, Texas Instruments debuted a 0.24 square micrometer 45 nm SRAM cell, with the help of immersion lithography.
  • In November 2006, UMC announced that it had developed a 45 nm SRAM chip with a cell size of less than 0.25 square micrometer using immersion lithography and low-k dielectrics.
  • In June 2007 Matsushita Electric Industrial Co., Ltd. started mass production of System-on-a-Chip (SoC) for use in digital consumer equipment based on the 45-nm process technology.

The successors to 45 nm technology will be 32 nm, 22 nm, and then 16 nm technology per ITRS.

Commercial introduction

Intel has shipped its first 45 nanometer based processor on the 5400-series Xeon(R) platform in November 2007.

Many details about Penryn appeared at the April 2007 Intel Developer Forum. Its successor is expected to be Nehalem. Important advances[2] include the addition of new instructions (including SSE4, also known as Penryn New Instructions) and new fabrication materials (most significantly a hafnium-based dielectric).

AMD has targeted its commercial production for 2008.

Intel's 45 nm Process

At IEDM 2007, more technical details of Intel's 45 nm process were revealed:

  • 160 nm gate pitch (73% of 65 nm generation)
  • 35 nm gate length (same as 65 nm generation)
  • 1 nm equivalent oxide thickness, with 7 Å transition layer
  • gate-last process using dummy polysilicon
  • 9 layers of low-k Cu interconnect, the last being a thick "redistribution" layer
  • contacts shaped more like rectangles than circles for local interconnection
  • lead-free packaging
  • 1.36 mA/um nFET drive current
  • 1.07 mA/um pFET drive current, 51% faster than 65 nm generation, with higher hole mobility due to increase from 23% to 30% Ge in embedded SiGe stressors


  1. ^ IEEE Spectrum: The High-k Solution
  2. ^ Report on Penryn Series Improvements.. Intel (October 2006).

Preceded by
65 nm
CMOS manufacturing processes Succeeded by
32 nm
This article is licensed under the GNU Free Documentation License. It uses material from the Wikipedia article "45_nanometer". A list of authors is available in Wikipedia.
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