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22 nanometer



CMOS manufacturing
processes

The 22 nanometer (22 nm) node is the CMOS process step following 32 nm. It is expected to be reached by semiconductor companies in the 2011-2012 timeframe. At that time, the typical half-pitch for a memory cell would be around 22 nm. The exact naming of this technology node comes from the International Technology Roadmap for Semiconductors (ITRS).

Additional recommended knowledge

The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point.

The 22 nm node is expected to be a significantly different technology from today's 65 nm and older technologies. Thus the path to 22 nm will be revolutionary rather than evolutionary.

Since photolithography requires introducing double patterning by the 32 nm node, it is likely that this approach will continue to be used at the 22 nm node, in conjunction with hyper-NA (numerical aperture) immersion lithography tools.

Some predictions for the 22 nm node come from the ITRS. For example, it is predicted that silicon devices will no longer be planar, but will require ultrathin sections mostly surrounded on the sides by gates. The silicon body in each section is fully depleted, i.e., the free charge carrier concentration is deliberately suppressed. The sections basically protrude as fins from the surface (sometimes these are known as FinFETs). The creation of fins is a new challenge for the semiconductor industry, which has become accustomed to building transistors on a flat silicon surface.

The successor to 22 nm technology will be 16 nm technology per ITRS.


Preceded by
32 nm
CMOS manufacturing processes Succeeded by
16 nm
 
This article is licensed under the GNU Free Documentation License. It uses material from the Wikipedia article "22_nanometer". A list of authors is available in Wikipedia.
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